1. Field of the Invention
The present invention relates to a semiconductor apparatus which includes a three-dimensional transistor and a production method thereof.
Priority is claimed on Japanese Patent Application No. 2007-150284, filed Jun. 6, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Because of requirements for a high integration in the semiconductor field, elements of the semiconductor apparatus have been being small and fine. Due to such requirements, a three-dimensional transistor has been developed in which elements are vertically arranged in order to integrate more elements in a smaller area compared to that of a conventional planer transistor.
There is a generally-known constitution of such a three-dimensional transistor called SGT (surrounding gate transistor).
In a constitution of SGT, for example, as shown in FIG. 13, a silicon pin 101 which constitutes a three-dimensional transistor is set on a substrate 100. The silicon pin 101 includes both a channel portion 102 and source/drain diffused layers 103 (upper diffused layer (drain diffused layer) 103a and lower diffused layer (source diffused layer) 103b) which are formed at an upper portion and lower portion of the silicon pin 101. The channel portion (a portion of p type Si) 102 provided at a center portion of the silicon pin 101 has a constitution in which the channel portion 102 is surrounded by both a gate insulation film 104 and a gate electrode 105. A source electrode 106 is provided under the lower diffused layer (source diffused layer) 103b which is provided under the channel portion 102. A drain electrode 107 is provided on the upper diffused layer (drain diffused layer) 103b which is provided above the channel portion 102. In other words, in the constitution of the silicon pin 101, the source/drain diffused layers 103 are provided on and under the channel portion 102.
Patent Document 1 discloses both a three-dimensional transistor which is obtained by controlling a depletion layer extending in a direction from the outside to the inside of the channel portion 102 and a DRAM (Dynamic Random Access Memory) including the three-dimensional transistor.
Patent Document 2 discloses a MIS (Metal Insulator Semiconductor) DRAM.
Patent Documents 3 and 4 disclose a semiconductor apparatus which includes a constitution of a memory cell by using such a three dimensional transistor.
FIG. 14 shows one example of a constitution of a memory cell including a conventional three-dimensional transistor. Regarding this three-dimensional transistor, on a silicon substrate 200, multiple three-dimensional transistors 210 are arranged at even intervals on multiple bit lines 205 which are arranged in parallel in a vertical direction in FIG. 14. A pair of gate electrodes (word lines) 206a and 206b are arranged between the multiple three-dimensional transistors 201 and are arranged in a horizontal direction in FIG. 14 while crossing the bit lines 205.
Each of the multiple three-dimensional transistors 201 has a constitution in which the lower diffused layer 203b, the channel portion 202 and the upper diffused layer 203a are provided on the bit lines 205, and a capacitor 204 is provided on the upper diffused layer 203, and consequently, a memory cell is constituted.
[Patent Document 1] Japanese Patent Application, First Publication No. H5-160408
[Patent Document 2] Japanese Patent No. 2941039
[Patent Document 3] U.S. Pat. No. 6,150,687
[Patent Document 4] Japanese Patent Application, First Publication No. H05-136374
However, compared to a conventional planer transistor in which the electric potential or voltage of a channel portion is controlled by a substrate, in a constitution of a three-dimensional transistor shown in FIG. 14, even though the electric potential of the upper and lower diffused layers are controlled, the potential of a channel portion which is arranged between them is not controlled and is a floating area. Therefore, there is a problem in which the threshold voltage of the transistor is fluctuated (floating body effect) because of a positive electric charge at the channel portion caused by using the transistor. In order to avoid such a problem, regarding the memory cell shown in FIG. 14, a constitution is proposed in that one of the gate electrodes 206a and 206b is connected to the channel portion 202. However, in such a proposal, it is difficult to achieve high integration.